library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity SR2MUX_logic is
    port(SR2val: in unsigned(15 downto 0);
         Imm7: in unsigned(15 downto 0);
         IR_out: in unsigned(15 downto 0);
         SR2MUX_out: out unsigned(15 downto 0));
     end entity SR2MUX_logic;
     
architecture build of SR2MUX_logic is
    begin
        process(IR_out(7),SR2val,Imm7)
            begin
                if IR_out(7) = '0' then
                    SR2MUX_out <= SR2val;
                else
                    SR2MUX_out <= Imm7;
                end if;
            end process;
    end build;
         
